On Placement and Sizing of Sleep Transistors in Leakage Critical Circuits

Leakage power is increasingly gaining importance with technology scaling. Multi-Threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS technology for reducing leakage power. In this paper we present a fine grained approach where each gate in the circuit is provided an independent sleep transistor. Unlike other approaches, we do not perform any clustering. Key advantages of this approach include better circuit slack utilization and improvements in signal integrity (which is a major disadvantage in clustering based approaches). To this end, we propose an optimal polynomial time fine grained sleep transistor sizing algorithm. We also prove the selective sleep transistor placement problem as NP-Complete and propose an effective heuristic. Finally, in order to reduce the sleep transistor area penalty (which might get high since clustering is not performed), we propose a placement area constrained sleep transistor sizing formulation. Our experiments show that on an average the sleep transistor placement and optimal sizing algorithm gave 69.7% and 59.0% savings in leakage power as compared to the conventional fixed delay penalty algorithms for 5 and 7 % circuit slowdown respectively. Moreover the post placement area penalty was less than 5% which is comparable to clustering schemes [9].